1. Field of the Invention
The present invention relates generally to methodology of making semiconductor devices and, more particularly, to a semiconductor device fabrication method which requires a thin-film polishing process or processes.
2. Related Art
In recent years, advanced microfabrication technologies are newly developed to meet the need for increased integration densities and higher performances of ultralarge-scale integrated (ULSI) semiconductor circuit devices. In particular, in order to achieve high speed performances for LSI chips, attempts are recently made to replace electrical wiring material from traditionally used aluminum (Al) alloys to copper (Cu) with low resistivity or Cu alloys (collectively referred to as “Cu” hereinafter). In view of the fact that Cu is difficult in microfabrication by means of dry etch techniques, which have frequently been used in the formation of Al alloy wires, the so-called damascene method is used in most cases to form buried or “embedded” on-chip lead wires by depositing a Cu film on an insulative film with trench-like grooves defined therein and then removing by chemical-mechanical polish (CMP) techniques its selected portions other than groove-buried film portions. Typically the Cu film is such that after having formed a thin seed layer by sputter methods, electrolytic plating is applied thereto to form a multilayered film having a thickness of several hundred of nm. In the case of forming a multilayered Cu wire pattern, an alternative method is employable for forming wires of the type having the so-called “dual damascene” structure. This method has the steps of depositing an insulative or dielectric film on its underlying wires, defining therein certain openings called “via holes” and trenches (wiring grooves) for upper-layer wire use, burying a film of chosen wiring material, such as Cu, both in the via holes and in the trenches at a time, and removing unnecessary overlying Cu portions by CMP to thereby planarize the film surface, resulting in formation of the intended buried wires.
Recently, consideration is given to using as an interlayer dielectric (ILD) film a film of specific insulative material which is low in dielectric constant, known as the low dielectric constant k or “low-k” film. More specifically, attempts are made to reduce the parasitic capacitance between wires by use of a low-k film having its relative dielectric constant k of 3.5 or below, which is lower than the relative dielectric constant, e.g., about 4.2, of silicon oxide films (SiO2 films).
Unfortunately the low-k film has in many cases a porous structure in order to achieve such extra-low dielectricity, resulting in a decrease in physical or mechanical strength. Accordingly, during chemical-mechanical polishing (CMP) of a Cu film, particles attached to the bottom or back surface of a semiconductor substrate can be detached or “liberated” to move onto the substrate's top surface. If this is the case, the particles act as start points of occurrence of Cu-film peeling and/or scratching defects. Once such defects take place, it is no longer possible to form electrical interconnect wires of high quality.
In currently available semiconductor device fabrication processes, CMP is applied to a semiconductor substrate at various stages other than the Cu wire forming step, which include, but not limited to, forming a shallow trench isolation (STI) structure, forming an insulative film on or above resultant device, and defining interlevel connection studs or “plugs” in the insulator film. When performing these CMP processes, if contaminant particles are attached to the back surface of a substrate, then the film peel-off and scratching can occur at the film thus processed in the way stated above.
As ultralarge-scale integration (ULSI) chips increase in integration and in performance, the minimum feature size of on-chip wires is decreased to a level of 90 nanometers (nm) or less. This wire width shrinkage makes it more difficult to well control the size dimensions thereof. Similarly, in the formation of onchip circuit elements which underlie the wires also, the size control appreciably increases in difficulty. The accuracy of such wire size is much influenceable by the precision of exposure size in lithography processes. Thus, in order to obtain the intended focal depth large enough to accomplish successful exposure, a need is felt to exhaustively remove any residual contaminant particles on a semiconductor substrate-supporting stage or “table” of exposure equipment. However, particles are still attachable to the back surface of a semiconductor substrate. Due to the presence of such particles, chuck errors can occur in the event that the substrate is chucked. This makes it impossible to perform chucking on the stage. In the worst case, any intended exposure is hardly executable.
Prior known approaches to avoiding the problem occurring due to residual contaminants attached to the back surface of a semiconductor substrate include a technique (as disclosed for example in JP-A-2000-150640) for removing metallic contaminants residing on the back surface of a semiconductor substrate during fabrication of a multilayer wiring pattern, which has the steps of forming a barrier film on the substrate back surface and, after having formed the multilayer wires, selectively removing the barrier film by CMP to thereby prevent such metal contaminants from diffusing thereafter into the substrate. Another technique is found in JP-A-2004-288870, which is for cleaning and removing by chemical solutions the barrier film together with the metal contaminants after having formed multilayer wires to thereby preventing subsequent outdiffusion of the metal contaminants into the substrate.
However, these techniques fail to provide a remedy for successful removal of those residual particles as attached to the back surface of a semiconductor substrate during CMP-based processes, for example, at the time the multilayered wires are formed and, for this reason, are incapable of bringing solutions to the problem as to the occurrence of film peel-off and scratch defects.